1. Field of the Invention
The invention relates in general to a compatible interface and a controlling method of a peripheral component interconnection (PCI) bus. More particular, the invention relates to an interrupt processing method and a compatible hardware of a PCI bus.
2. Description of the Related Art
Currently, the PCI bus is used as the main bus for connecting a peripheral interface in a computer motherboard. Only the master or the main bridge in the PCI bus can initiate data transaction. The PCI compatible component to initiate a read or write transaction is called an initiator. The corresponding transaction object is called the target. The data transaction between the PCI compatible components is controlled by the interface controlling signals such as a cycle frame (FRAME) signal, an address/data bus (AD) signal, a command/byte enable (CBE[3:0]) signal, an initiator ready (IRDY) signal, a target ready (TRDY) signal and a stop (STOP) signal.
The FRAME is output from the initiator to indicate the start and lasting period of access. When the FRAME is output, the data transaction via the PCI bus starts. When the FRAME is maintained at a low potential, that data transaction continues. Meanwhile, a valid address is output from the address/data bus (AD) signal during the address cycle. A valid bus command (that meets the PCI specification) is output from the CBE[3:0] to instruct the target what the data transaction type is required by the initiator. The CBE[3:0] line comprises 16 different bus commands encoded with four bits, this is specifically defined in PCI specification. After the valid address, the data is output from the address/data bus, and the cycle is called the data cycle. At the same time, the CBE[3:0] line outputs the byte enable signals of the transmitting data. The IRDY signal and the TRDY signal are used to respectively instruct that the initiator and the target are ready to perform data transmission. For example, during the read operation, the IRDY signal instructs that the initiator is ready to receive data, and the write operation, the TRDY signal instructs that the target is ready to receive data. Regarding STOP signal, the target is used to request the initiator to stop the current data transaction. When the output of the FRAME signal is stopped, it means that the transaction status is to transmit the last data or the last data has been transmitted.
Apart from the above interface control signals during data transaction, the PCI bus further defines four interrupt signals: INTA, INTB, INTC and INTD. When any of the peripheral components of the PCI bus requires the driving program to process, these interrupt signals can be used to catch the attention. However, as the PCI bus has more than one peripheral component, the interrupt signals are thus the limited resources. It is thus inevitable to share the interrupt signals. When an interrupt occurs, the interrupt service routine has to inspect the status of the peripheral components to determine which peripheral component causes the interrupt as a reference to assign the control to the exact peripheral component driving program. A great burden is thus caused to the software.
FIG. 1 shows a structure of a PCI bus compatible system used in a personal computer motherboard. The conventional personal computer motherboard comprises a control chip set 100, a dynamic random access memory 110, a central processing unit (CPU) 120, a PCI bus I 130, and peripheral components 150. The control chip set 100 comprises a south bridge chip 102 and a north bridge chip 104. Many of the conventional high level motherboards further comprise a PCI—PCI bridge 140, a PCI bus II 160 and peripheral components 170 located in the second level.
When any of the peripheral components 150 requires an interrupt service routine to process, a memory write transaction is started, and the data to be processed is written into the dynamic random access memory 110 via the control chip set 100. Meanwhile, one of the four interrupt signals of the PCI bus is output by the peripheral components 150 to cause the attention of the system. The control chip set 100 has to output an exact interrupt signal INTR to the central processing unit 120, so that the central processing unit 120 can process the data to be processed. It is well known that, based on the consideration of performance, a PCI bus is a multiplex system that allows many masters to control. When the control chip set 100 starts the memory write transaction, it does not indicate that the data to be processed has been written to the dynamic random access memory completely. The data to be processed can be stored in the buffer of the control chip set 100 without being written into the dynamic random access memory 110. The buffer in the control chip set 100 may store multiple bits of data output from different peripheral components. If the data to be processed, which is not completely written into the dynamic random access memory 110, is processed by the central processing unit 120 writing the data to be processed into the dynamic random access memory 110, an error may be caused. This is a situation, which is not allowed to happen.
One conventional method to resolve the above problem is to control the timing of the interrupt signal INTR, which is generated by the control chipset 100, to the central processing unit 120. Before the data to be processed is completely written, the generation of the interrupt signal INTR is prohibited. Since the buffer may store multiple bits of data belong to different peripheral components, and the control chip set 100 cannot determine which data is the data to be processed, the interrupt signal INTR is not allowed to generate. It is thus cause a delay for the generation of the interrupt signal INTR to affect the performance. It is well known that when the buffer is deeper, the write-buffer latency is longer. Especially in the current control chip set 100, the write-buffer latency is more significant since the south bridge chip 102 is responsible for controlling the PCI bus 130, and the north bridge chip 104 is responsible for controlling the dynamic random access memory 110. When the peripheral components 170 require an interrupt process via the multiple level PCI bus structure, it is even more difficult to estimate the write-buffer latency.
Another conventional method is to control the timing for the central processing unit 120 to process the data to be processed. The central processing unit 120 has to inspect the status of the peripheral components as a reference for interrupt process. According to the ordering rules of PCI (read cannot pass posted write data), by this method, the central processing unit 120 has to wait until the data to be processed to be written completely and inspects the status of the peripheral components. However, in this method, in addition to the problem of the above write-buffer latency, the performance of the system is seriously affected since the read cycle of a general central processing unit does not have the function of pipeline.
In the specification of PCI bus 2.2, an optional interrupt method called message signaled interrupt (MSI) is provided. By writing a system specified message from the peripheral component to the system specified address, that is, to write the system specified message to the system specified address of the PCI bus as the system specified address of the memory write transaction. The system specified message and address are initialized during the device configuration of the PCI bus. However, the current system to support the message signaled interrupt uses the same address for the system specified address to reduce the flexibility of processing multiple system specified messages of the peripheral components in the same interrupt service routine. The remaining flexibility is to use the 16-bit system specified message to represent 16 various possible reasons that cause the message signaled interrupt. In the current system, the problem of write-buffer latency has not been resolved, so that other conditions may occur, for example, the new message of the system specified message may overwrite the old system specified message due to long write-buffer latency.